As a result of explosive popularization of the Internet, the table scale required for a router and a switch in the network has been rapidly increasing, and the improvement of the search speed of the table has been demanded. For the achievement of this demand by means of hardware, ternary content addressable memory (TCAM) has attracted a lot of attention.
FIG. 19 schematically indicates the configuration of a router. In FIG. 19, an example comprised of a network interface NIF, a network processor NP, a search engine SE, a search table LUT, and a content memory CM is shown. The network interface NIF and the network processor NP are connected by a system bus SBS. The network processor NP and the search engine SE are connected by an internal bus IBS. The search engine SE and search table LUT are connected by a data bus DQ. Here, the search table LUT is TCAM and the content memory CM is a static random access memory (SRAM) or a dynamic random access memory (DRAM).
The router transfers a packet from the Internet network IPN via the network interface NIF. The network processor NP decodes and reconstructs the content of the received packet. For example, the destination Internet protocol address (IP address) read from the packet header is transferred to the search table LUT via the search engine SE. The search table LPT stores a plurality of destination IP addresses, and when the inputted destination IP addresses are stored, it generates the address for reading the information corresponding to the destination IP address from the content memory CM. The content memory CM stores route information necessary for packet transfer and port number of the router and outputs information corresponding to the address inputted via the content memory address bus CADD to the network processor NP via the content bus CBS and the search engine SE. The network processor NP reconstructs the header content based on the information and transfers a packet to the next relay point from the designated port.
IEEE Journal of Solid-state circuits, vol. 31, No. 11, November 1996, pp. 1601 to 1609 (non-patent document 1) describes the TCAM cell configuration in TCAM. FIG. 20 shows the cell configuration of FIG. 1 of the non-patent document 1. This cell comprises the following three circuit blocks. The first circuit block is a memory cell SMC31 which comprises NMOS transistors N311, N312, N313, and N314 and PMOS transistors P311 and P312 as is the case of so-called SRAM cell. The second circuit block is a memory cell SMC32 which comprises NMOS transistors N321, N322, N323, and N324 and PMOS transistors P321 and P322 like the memory cell SMC31. The third circuit block is a comparator circuit MUC which comprises NMOS transistors N331, N332, N333, N334, and N335. The memory cell SMC31 stores binary information of zero or one (0, 1) and the memory cell SMC32 stores the third information “X” which is so-called “don't care” state, respectively. The information described above can be written and read by selectively activating the word line WL31 or WL32 as is the case of the publicly known SRAM. In addition, the comparator circuit MUC carries out XNOR operation to compare the storage information with the input information.
As an example, the search operation when memory information is “1” is described below. In this case, assume that the storage node NT in memory cell SMC311 is driven by power supply voltage VDD and the storage node NB is driven by ground voltage VSS. In the case where the TCAM cell is not in the “don't care” state and the storage node DC in the memory cell SMC32 is driven by the power supply voltage VDD, the transistors N331, N335 in the comparator circuit MUC become conductive, respectively, and the transistor N332 is in the cut-off state. Under the condition as described above, when inputting information “1” after precharging the match line ML to the voltage higher than the ground voltage VSS, the bit line BLB of the bit lines BLT and BLB which are at the ground voltage VSS is driven by the power supply voltage VDD, and the transistor N334 in the comparator circuit MUC is brought into the conductive state. However, since the transistor N332 is in the cut-off state, the condition between the match line ML and the grounding electrode is kept open. Consequently, by discriminating the voltage of the match line ML held to the precharge voltage with a match line sense AMP (not illustrated), it is determined that the compared information is matched.
On the contrary, when inputting information “0”, the bit line BLT of the bit lines BLT and BLB which are at the ground voltage VSS is driven by the power supply voltage VDD, and the transistor N333 in the comparator circuit MUC is brought into the conductive state. Consequently, since the match line ML and the ground electrode are short-circuited via the transistors N335, N331, and N333, the match line ML is discharged. That is, by discriminating voltage drop of the match line ML with the match line sense AMP, it is determined that the compared information is mismatched. Note that, when the TCAM cell in the drawing is in the “don't care” state, since the storage node DC in the memory cell SMC 32 is driven by the ground voltage VSS, the transistor N335 in the comparator circuit MUC is cut off. Consequently, since no current route is formed between the match line ML and the ground electrode, even if any information is inputted, the match line ML is held to the precharge voltage and it is forcibly determined that the compared information is matched.
In addition, even when the input information is the third information “X” which indicates the so-called “mask” state, since both bit lines BLT and BLB are held to the ground potential VSS, the transistors N333 and N334 in the comparator circuit MUC are cut off. Consequently, even if the memory cell SMC31 stores any information, since no current route is formed between the match line ML and the ground electrode, the match line ML is held to the precharge voltage and it is forcibly determined that the compared information is matched.